1. Field of the Invention
The present invention relates to a semiconductor memory which Can attain a fast and stable data reading operation.
2. Description of the Related Art
As the semiconductor production techniques have been greatly improved recently, semiconductor memories have become more densely integrated and contain a larger memory capacitance. However, a semiconductor memory with a larger memory capacitance requires a longer time to read information stored therein. It is necessary to shorten the delay time of the input/output portion in the semiconductor memory to realize a high speed operation.
FIG. 13 shows a typical circuit structure of a conventional semiconductor memory 1300.
An address signal input via a bus or the like is fed to an X decoder 1302 and a Y decoder 1303 via an address input buffer circuit 1301 to indicate a particular piece of data on a memory cell array 1304. The data on the memory Cell array 1304 indicated by the address signal is read by a sense amplifier 1305 and output to the outside via an output buffer circuit 1306.
The address signal input by the address input buffer circuit 1301 is also fed to an address input detecting circuit 1307. Upon detecting a change of the input address signal, the address input detecting circuit 1307 puts a timing signal generating circuit 1308 into operation on the basis of the timing for detecting the change. The timing signal generating circuit 1308 generates control signals such as a precharge signal .phi..sub.1 and an output buffer stopping signal .phi..sub.2. The precharge signal .phi..sub.1 precharges bit lines (not shown) of the memory cell array 1304 before reading data. The output buffer stopping signal .phi..sub.2 stops the operation of the output buffer circuit 1306 during a predetermined period of time during which the sense amplifier 1305 reads a piece of data in the memory cell array 1304.
An output enable signal is input to an output buffer control circuit 1310 via an output enable input buffer circuit 1309. The output enable signal controls the output buffer circuit 1306 from the outside. The output buffer control circuit 1310 outputs an output buffer operating signal OE that becomes non-active when the output enable signal becomes non-active or when the output buffer stopping signal .phi..sub.2 becomes active. When the output buffer operating signal OE is active, the output buffer circuit 1306 outputs the data read by the sense amplifier 1305 to the outside. When the output buffer operating signal OE is non-active, the output buffer circuit 1306 stops outputting the data.
FIGS. 14 and 15 show waveforms of each signal used in the semiconductor memory 1300. The operation of the semiconductor memory 1300 will now be described referring to FIGS. 14 and 15.
A change of the address signal causes changes of output signals A.sub.i and A.sub.j output by the address input buffer circuit 1301. In response to the changes of the output signals A.sub.i and A.sub.j, the X decoder 1302 and the Y decoder 1303 start operating and the address input detecting circuit 1307 puts the timing signal generating circuit 1308 into operation. A low to high transition (a transition to be active) of the precharge signal .phi..sub.1 results in precharging the bit lines (not shown) of the memory cell array 1304. Then, the sense amplifier 1305 reads data from the memory cell array 1304. The output buffer stopping signal .phi..sub.2 is at a high level (active) during a predetermined period of time, resulting in keeping the output buffer operating signal OE at a high level (non-active) during the predetermined period. Then, when the output buffer stopping signal .phi..sub.2 undergoes a high to low transition (becomes non-active), the output buffer operating signal OE undergoes a high to low transition becomes active). As a result, the output buffer circuit 1306 starts outputting the data read by the sense amplifier 1305.
A high to low transition of the output enable signal (a transition to be active) causes a high to low transition (a transition to be active ) of the output buffer operating signal OE as is shown in FIG. 15. As a result, the output buffer circuit 1306 starts outputting the data read by the sense amplifier 1305.
Each of the address input buffer circuit 1301 and the output enable input buffer circuit 1309 is constituted by a CMOS inverter circuit as shown in FIG. 16. An inverted voltage V.sub.INV (FIG. 17) of the CMOS inverter circuit can be set by selecting respective circuit parameters of a PMOS transistor and an NMOS transistor included in the CMOS inverter circuit. For example, when the CMOS inverter circuit receives an output level from a TTL, the inverted voltage V.sub.INV is set so that an output signal V.sub.OUT undergoes a low to high transition whenan input signal V.sub.IN is less than 0.8 V (V.sub.IL), and that the output signal V.sub.OUT undergoes a high to low transition when the input signal V.sub.IN is more than 2.2 V (V.sub.IH) as is shown in FIG. 17.
FIG. 18 shows the dependency of the inverted voltage V.sub.INV on a supply voltage V.sub.CC. As is shown in FIG. 18, the inverted voltage V.sub.INV rises as the supply voltage V.sub.CC rises. As a result, the higher the supply voltage V.sub.CC becomes, the smaller the difference between the voltage V.sub.IH and the inverted voltage V.sub.INV (V.sub.IH -V.sub.INV) becomes. Thus, it is difficult to secure a noise margin of a sufficient size. When the noise margin has such a small size and an internal ground potential GND becomes unstable, levels of input signals can be misjudged.
For example, when the output buffer circuit 1306 starts operating, a large current transitionally occurs, which makes the internal ground potential GND temporarily unstable. Such transient of the internal ground potential GND can cause changes of the levels of the output signals A.sub.i and A.sub.j output by the address input buffer circuit 1301. In such a case, the address input detecting circuit 1307 misjudges this change to be a change in the address signal. As a result, the data reading operation is performed in error as is shown in FIGS. 14 and 15 by dashed lines.
In order to avoid the above-mentioned malfunction, in a conventional semiconductor memory, the driving ability of the output buffer circuit 1306 is limited to minimize the instantaneous current and the response property of the address input buffer circuit 1301 is degraded. Thus, the change of the address signal is not detected in error even when the internal ground potential GND becomes rather unstable. Accordingly, the conventional semiconductor memory has a problem that a high speed operation must be sacrificed to attain a stable operation.